News

IEEE4d
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements
Chains of MOBILE gates have been fabricated and the experimental results of their correct operation with a two-phase clock scheme are provided. As far as we know, this is the first working MOBILE ...
IEEE5d
A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS
Abstract: This paper presents an asynchronous pipelined all-digital 10-b time-to-digital converter (TDC) with fine resolution, good linearity, and high throughput. Using a 1.5-b/stage pipeline ...